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Altera_Forum's avatar
Altera_Forum
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13 years ago

Simulation using ModelSim

Hi.. i am simulating a project using modelsim i am facing some problems 1. i have written a test bench for my simulation and assigning some data at input port witch is 8bit wide and suppose to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

well post some code and your testbench and we'll see.

With a testbench you can do a load of stuff you cannot do in synthesisable VHDL, so its very easy to control data flow.