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Altera_Forum's avatar
Altera_Forum
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14 years ago

simulation unexpected output

Hi everybody,

I'm currently writing some vhdl just for my own personal interest and i have a signal that I want to be a '0' or '1' based on some integer input, here's the line of code:

cout <= '1' when variable_length_int /= 0 else '0';

and everything works fine except when the signal should be '0' in the simulation it turns to unknown instead.

I've tried a few ways around this, having a constant zero signal assigned instead of just '0', switching it to "cout <= '0' when variable_length_int = 0 else '1';" neither of which has changed the behavior in simulation

one idea is if I could OR all the digits of this integer (in a generic way) but I dont know how to do that just yet either

so i have 2 questions, why is the signal unknown when it should be zero, and is there a way in standard IEEE vhdl to OR individual bits of an integer or signal in a generic way (like a signal thats a bit vector 0 to n-1)?

thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Im guessing that you drive cout to '1' elsewhere in the code. std_logics can be driven from multiple sources, and they resolve depending on the multiple drivers.

    For example, if you did this:

    cout <= '1';

    cout <= '0';

    you will get 'X'.

    But if you did this:

    cout <= '1';

    cout <= '1';

    you will get '1', hence my theory you have multiple drivers on cout.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    TO answer your second question - a VHDL integer type has no bits, so you cannot OR it with anything. You have to convert it to an array type that can have its bits ORed.

    lucky, VHDL provides the unsigned/signed types which are arrays of std_logic, and keep the numericness of the number. you can OR std_logic_vectors, but then std_logic_vectors are NOT numbers that you can do arithmatic with.

    for the conversion: make sure you include the numeric_std package (delete the std_logic_arith and std_logic_unsigned packages if you are using them - they are not standard libraries). also, include the std_logic_misc library for a useful or_reduce function. then you can do this: 

    
signal some_int_slv : std_logic_vector(7 downto 0);
signal all_bits_reduced : std_logic;
...
some_int_slv <= std_logic_vector( to_unsigned( variable_length_int, 8) );
all_bits_reduced <= or_reduce(some_int_slv);