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Altera_Forum's avatar
Altera_Forum
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14 years ago

simulation unexpected output

Hi everybody, I'm currently writing some vhdl just for my own personal interest and i have a signal that I want to be a '0' or '1' based on some integer input, here's the line of code: c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Im guessing that you drive cout to '1' elsewhere in the code. std_logics can be driven from multiple sources, and they resolve depending on the multiple drivers.

For example, if you did this:

cout <= '1';

cout <= '0';

you will get 'X'.

But if you did this:

cout <= '1';

cout <= '1';

you will get '1', hence my theory you have multiple drivers on cout.