simulation unexpected output

TO answer your second question - a VHDL integer type has no bits, so you cannot OR it with anything. You have to convert it to an array type that can have its bits ORed.

lucky, VHDL provides the unsigned/signed types which are arrays of std_logic, and keep the numericness of the number. you can OR std_logic_vectors, but then std_logic_vectors are NOT numbers that you can do arithmatic with.

for the conversion: make sure you include the numeric_std package (delete the std_logic_arith and std_logic_unsigned packages if you are using them - they are not standard libraries). also, include the std_logic_misc library for a useful or_reduce function. then you can do this:

signal some_int_slv : std_logic_vector(7 downto 0);
signal all_bits_reduced : std_logic;
...
some_int_slv <= std_logic_vector( to_unsigned( variable_length_int, 8) );
all_bits_reduced <= or_reduce(some_int_slv);