simulation performance

Hi Baldur

A few suggestions (some repeated from previous replies):

1) Try a different simulator - e.g. Modelsim (personally I hate it but hey it's free with the Altera bundle).

2) Try breaking the design down and simulating in pieces

3) Try a more elaborate testbench which includes self checking - i.e. apply stimulus (wait if necessary), check output, if output different to expected report an error - in VHDL this last bit can be done easily with the "assert" command. I'm not sure how this report gets shown in quartus but in modelsim and other dedicated simulators (e.g. ActiveHDL which I love) your message gets displayed in the console.

This last approach has the advantage that you don't have to wade through 10ms of waveforms looking for a fault - the console message tells you when the fault ocurred and you can dive straight in at the right point and have a look.

In VHDL the "assert" function doesn't get synthesised so you can even put this in your RTL code - not just your testbench. You can also mask it off from synthesis with the "translate synthesis_off" and "..._on" pragmas (if you want to).

Half an hour for 10ms worth of 200MHz clock doesn't sound too out of the ordinary (it always depends on the size of your code and clock speed, but I don't think you're an order of magnitude out), so maybe you might benefit from a different approach to simulation.

Personally I do as much self checking in the code and testbench as I can; and I simulate small chunks in detail so that a simulation of the whole design is mainly checking that the interfaces between my chunks are correct - the self checking makes this easier. Self checking and "assert" has the advantage that you can leave a design running and throw random data at it overnight and come morning you just check the console to see if you've had any errors. It takes a bit more time to set up your simulation like this but it pays off over the project.

Hope this helps