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Altera_Forum
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15 years ago

simulation from schematic file

Hello, I test Quartus II 10.0 web edition (SP1) and the native link with Modelsim-Altera. I created a counter in a vhdl file and integrated it in a schematic file (bdf) ; because i find th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i'm not sure that .bdf to HDL ever used more than std_logic and std_logic_vector. complex types (even integer) are easiest to "flatten" down in to std_logic and std_logic_vector. you can also see this in SOPC Builder where only std_logic and std_logic_vector are supported