Simulation fails when it goes into big design.

By the way, by your recommendation I've precalculated the count outside the process and surprisingly it has reduced the number of hold time and setup time violations. Still, there are some lingering around, what should I do about them?

    DB_T3PWM_proc: process(CLKOUT)
    variable counter_en    : STD_LOGIC;
    variable prev_T3PWM    : STD_LOGIC;
    variable count    : UNSIGNED (8 downto 0);
    begin
    
        if(rising_edge(CLKOUT)) then
-- if we see a transition, start the clock and enable deadband
            if(prev_T3PWM /= T3PWM) then
                counter_en := '1';
                count := EVB_count;
            end if;
                
-- if we've reached 0, stop counting and disable deadband
            if(count = "000000000") then
                counter_en := '0';
-- else decrement counter by one
            else
                count := count - 1;
            end if;
-- remember T3PWM for next time
            prev_T3PWM := T3PWM;
-- and output delayed PWM outputs
            PWMB7_DB_reg    <= T3PWM and not counter_en;
            PWMB8_DB_reg    <= not T3PWM and not counter_en;
        end if; -- if rising_edge(CLKOUT)
        
        if falling_edge(CLKOUT) then
        end if;
    end process DB_T3PWM_proc;