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Altera_Forum
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9 years ago

Simulation fails if Modelsim time resolution is not 1ps

I'm using Quartus Lite 16.1 and the free Modelsim Alters SE. I have a VHDL behavioral simulation that seems to work fine at the default 1ps resolution but if painfully slow. My clock period is 20 ns,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

PLL simulation used to require ps resolution, otherwise no output clock generated. Basic VHDL should be fine with 1 ns.

May be there's something special about your design.