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Honored Contributor
Honored ContributorSimulation fails if Modelsim time resolution is not 1ps
I'm using Quartus Lite 16.1 and the free Modelsim Alters SE. I have a VHDL behavioral simulation that seems to work fine at the default 1ps resolution but if painfully slow. My clock period is 20 ns,...
Altera_ForumHonored Contributor
Honored ContributorPLL simulation used to require ps resolution, otherwise no output clock generated. Basic VHDL should be fine with 1 ns.
May be there's something special about your design.
