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MCost7's avatar
MCost7
Icon for New Contributor rankNew Contributor
7 years ago

Simulation behavior didn't match with synthesized design

The quartus version 18.1 is used, the target FPGA is Stratix IV. The code that is not correctly synthesized is: assign addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000); But the simul...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

In First approach 'assign addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000);'

dst covers only two combinations : 3'b001 & 3'b000.

In Second approach dst covers multiple combinations : 3'b000 ,3'b111,3'b001 ,3'b011 etc.

So it`s obvious that variation in Quartus report.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)