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Altera_Forum
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17 years ago

Simulating ROM( MegaWizard Plug-in manager)

Hi, I am trying to implement a system in VERILOG which uses ROM: 1-PORT from the MegaWizard Plug-in Manager. I want to simulate the system using Modelsim-Altera. I converted the .mif fi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I've encountered this problem hours before. I copy the Hex file to the folder where the projects file is, and clear the path information in .v file, like altsyncram_component.init_file = "line_kbyte_buff.hex"

Then it can work. And the .ver files also generated after simulation. :D