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Altera_Forum's avatar
Altera_Forum
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13 years ago

simulating mixed VHDL and Verilog code in ModelSim

i'm simulating a testbench which is written in system verilog language in addition to the testbench i have 5 modules thet some of them are written in VHDL and some in verilog language when i want to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Yes, the full licensed versions of Modelsim and Questa support multiple languages; SystemC, VHDL, SystemVerilog, etc.

But it ain't free ...

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Even the standard full license doesnt support it, you need a specific mixed language license. :(