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Altera_Forum's avatar
Altera_Forum
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13 years ago

simulating mixed VHDL and Verilog code in ModelSim

i'm simulating a testbench which is written in system verilog language in addition to the testbench i have 5 modules thet some of them are written in VHDL and some in verilog language when i want to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes, the full licensed versions of Modelsim and Questa support multiple languages; SystemC, VHDL, SystemVerilog, etc.

But it ain't free ...

You can use Modelsim-ASE if you first use Quartus to output a Verilog netlist for your synthesizeable VHDL code. You can then run your SystemVerilog testbench with that code. You'll lose visibility into the internals of the design, but you can always run signals to I/O pins temporarily if needed ...

And hey, don't forget that you can always re-write your testbench in VHDL, or your code in SystemVerilog :)

Cheers,

Dave