Forum Discussion
Simulating communication over PCIE
- 5 years ago
Hi Luca,
Yes, I don't think this is feasible. The existing PCIe generated testbench and BFM provides a simple method to do basic testing of the application layer logic, and this is not intended to be a substitute for a full verification environment.
Hi,
Assuming you are targeting Arria 10 device, the simulator that supported is listed in Table 9 from the link below.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf
For your information, we don’t work on the Xillybus tool, so I afraid no much support can offer here.
Regards -SK
- lucadimauro5 years ago
New Contributor
Hi,
thank you for your reply SengKok.
What I'm asking is to know if I can simulate a PCIE block file on the host system connected to the simulated FPGA with vsim tool. But I think that it is not possible.
Regards,
Luca