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TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Simulating Altera IP Cores in Quartus Prime Lite 16.1 (or beyond)

Hi, I am working with a MAX10 and have instantiated the Soft LVDS core. I would like to use ModelSIM (the starter edition set up with NativeLink directly from Quartus) to simulate the behavior. Howev...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Have you instantiated the 'Soft LVDS core'module in main design?

Before compilation of project, create hdl file/inst. file for used IP & instantiate in main design.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)