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mmare6
New Contributor
New ContributorSimulate ADC PLL FPGA MAX10
On this video I try simulate PLL https://youtu.be/Yf15rAGqxQw My target is to simulate the ADC module. But at the moment simulation of the PLL module does not work. what am I doing wrong ??
mmare6New Contributor
New Contributorthank you for the support.
Below I will explain my mistakes
And I show what I corrected that the simulation started correctly.
remove *.sip file from project
1 Option change to Verilog HDL 1 ps
2 Add testbench. TestBench name is important. Must be The same as top level entity
on this video I show step by step how to do it correctly https://youtu.be/YbOnfNFJg6Y
