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I'm nut even sure how this code can run in a simulator without any errors but you should maybe check your algorithm first. In this line
sum:=sum + x(k)*y(n-k);
(n-k) can take a lot of values outside of the range 0 to 1, and that should cause an error in the simulator real quick.
You do realize that this code isn't synthesizable on real hardware, don't you?
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thank you for your reply
actually i want to simulate an upsampler (in DSP); and for implemet this ,i need to implement a convolution function,therfore i used that vhdl code(that is sent) and that is wrong. i don't know how can do it;please help me
thank you
hello,i changed my vhdl to the following code,but the output remains 0 and dosen't change when the inputs change,where is my mistake??
package mypack is
type real_vec is array(integer range <> ) of real;
end mypack;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.mypack.all;
entity conv1 is
generic (m:integer :=3;
n:integer :=1);
port (x:in real_vec(0 to m);
y:in real_vec(0 to n);
f:out real_vec(0 to m+n));
end conv1;
architecture Behavioral of conv1 is
signal h : real_vec(-(m+n) to m+n):=(others =>0.0);
--signal h : real_vec(-m to n):=(others =>0.0);
signal sum:real:=0.0;
begin
process (x,y)
begin
h(0 to n) <=y;
for i in 0 to m+n loop
for k in 0 to m loop
sum <= sum + x(k)* h(i-k);
end loop;
f(i) <= sum;
sum <=0.0;
end loop;
end process;
end Behavioral;
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