Provided that one has a file that is to be transmitted down to the FPGA and it will store every byte into internal or external memory (maximum size is around 1MegaByte). What is the preferred way of doing this? Should one create a custom solution in whic the user sends the file down serial port from PC, the FPGA recieves it into a FIFO and then it stores it in internal/external memory on a per-byte or per-byte-block basis. Or is it possible to utilize the JTAG port for this purpose such that the file can be streamed down the JTAG port and the design inside the FPGA can process the bytes as stated above? I expected this to be a simple problem since we already transmit configuration data to the FPGA and possibly a connected configuration memory device. However, it seems that it is not. :|

Hi, you can use the JTAG-UART IP Core. It simulates a UART interface via JTAG. Have a look at page 53. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf If you use UART for such a huge file, you should implement an error correction functionality. For example use Checksums and request invalid data again. The easiest way should be using a NIOSII. Greets Olaf

I take this to mean that no reference design exists for this purpose, you mean that the error correction can be implemented in software in a nios II? since the issue of checksum has been raised, do you mean that there should be checksum for the whole file or for chunks e.g every 256 bytes? Certainly the checksum shall have to be generated and stored within the file itself too. UART does not have a means to send acknowledge signal but RS232 may have it. Now specifically what do you imagine would be the application used to transmit the file from PC to the FPGA? I assume you envision a custom application.

On a second thought, as far as I vaguely understand, there is also a method by which such extra data can be bundled together with the FPGA configuration data and together with this configuration data be burned onto a configuration memory. Perhaps this will be a faster way to get this data onto a flash so the design can read it out and send it to the data converters?

Hi Xaui, I am searching for an answer to this same question. In particular, Altera's Frame Reader VIP IP core accesses an image stored in SDRAM. It's likely that anyone implementing a circuit including that Frame Reader might have wanted to copy a BMP or TIF from the PC's file system into SDRAM. I would expect there to be an out-of-the-box solution by now. Have you found a good answer? Hopeful thanks ...

PCIe would be the obvious choice, but that's complicated and potentially expensive if you're not using a device that has the hard PCIe IP built in. For simple and cheap you can't beat a UART. In this case you can't read the file out of PC memory, you would need an application on the PC transferring the file to you using the UART. But you can use terminal emulators like Teraterm to do this. UARTs are slow, but pretty darn easy to implement and to debug. You can at least star there to get the ball rolling and then upgrade to improve performance as needed. Bob

Simplest method to transmit a file to FPGA

13 Replies

Altera_Forum
Honored Contributor
9 years ago
You can use system console for this with a JTAG to avalon master: https://www.altera.com/en_us/pdfs/literature/hb/qts/qts_qii53028.pdf

There are APIs called "master_read_to_file" and "master_write_from_file" that you can use to push a file down to memory in the FPGA and vice versa for the opposite direction. I also used to use Nios II for this sort of thing with something called host FS where I could have Nios open a file up on the host for read/write purposes over the JTAG channel but I have no clue if that's still supported. I suspect system console can move the data faster than host FS since I seem to recall host FS was only around 4kB/s back with the first generation USB blaster.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
On a second thought, as far as I vaguely understand, there is also a method by which such extra data can be bundled together with the FPGA configuration data and together with this configuration data be burned onto a configuration memory. Perhaps this will be a faster way to get this data onto a flash so the design can read it out and send it to the data converters?
--- Quote End ---

Don't know if this is still an issue for you but to bundle the data with configuration image, use the convert programming files... utility and click add hex data; select relative addressing and check the set start address checkbox - enter the location in the configuration flash where you want the file (after the configuration image); click browse (...) in the hex file sub-window and browse for your Intel-hex formatted data file and click ok. Since you say the file is >1MB, use 32-bit addressing when you generate the data file.
Altera_Forum
Honored Contributor
9 years ago
G'day dglazar,

Thank you for this suggestion. That's a good idea! Bundling the image BMPe with the rest of the configuration data, and allow Quartus Programmer to install it for me, would be easier than manually transferring the file to SDRAM before each run. (I know it initializes on-chip memory, but does Quartus also pre-write SDRAM?)

My first project is a baseline iPipe into which I will subsequently insert the Circuit Under Evaluation.

Ultimately, we'll want to connect a camera to the front end.
For starters, I need to be able to play with a variety of 1080p test images.
So manually downloading is OK.

Thank you again for taking the time to comment on this issue.

Cheers --todd

Forum Discussion

Simplest method to transmit a file to FPGA

13 Replies

Recent Discussions

Quartus Dark Theme on Linux - Solution

Agilex3 - unknown IDCODE

jtagserver.exe causing BSOD together with ftdi driver

Tensor block usage

When you double click on a word, the other instances do not highlight due to the Find Box being open