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Altera_Forum
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9 years ago

Signed Addition in VHDL

Hi everyone, I want to implement an addition operation using VHDL. I have one input that comes from my Nios. this value is calculated in float format, then it sent to the VHDL block that i want...
Altera_Forum's avatar
Altera_Forum
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9 years ago

You said the inputs are floating point - signed treats the value as fixed point which is fundamentally different. If you insist on floating point, you'll have to use a floating point function from the IP catalog. It uses way more logic than a fixed point adder.