Honored Contributor
Honored ContributorThe said behaviour can indicate, that the PLL looses lock after device configuration respectively an asynchronous reset. In this case, the configured phase relation of PLL output clocks isn't valid any more. If so, the problem doesn't only affect SignalTap.
Another possible reason would be, that setup- and hold times for the SignalTap acquisition are violated. SignalTap may sample arbitrary levels then, possibly changing with small temperature or supply voltage modfications. Generally, I don't think that SignalTap is able to measure clock duty cycles with the intended accuracy. I also don't see a reason to doubt the configured duty cycles, that are defined by very basic parameter settings, that can be always checked in the fitter report.
