Honored Contributor
Honored ContributorHi again FvM,
as wrote in my previuos post I made the samplig clock faster (240 Mhz) but I have the same problems. One of these problems is that the "weird-shown" signals, for example the clocks, are shown with a duty cycle different that 50% when they were supposed to be 50% (at least, from the megafunction setup) If I had a constant error (like the clock duty cycle for example) I was almost sure that everything is caused by an error in my code, but what is leaving me with lot of doubts is that with the same .sof and .stp file (same compilation, no changes at all) programming in 2 different moments my FPGA (or running the STII in differnent moments) I get different results... anyway, thanks again for your help! C
