Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

SignalTapII reliability

Hi All, I ahve a question / doubt about Signal Tap II (STII) reliability : I'm doing some tests on a Stratix II GX FPGA mounted on a custom board, which is receiving datas from an optical connecti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hi FvM,

you are right at all when you say "..it seems to me, that you didn't yet consider the effect of sampling SignalTap input data with the resepctive sampling clock..."

In fact I didn't describe this setup in my STII file: I am using a 160 Mhz clock to sample my data lines. Do you think it is not enough? Anyway as soon as possible I will try to recompile my project with a higher freq. sampling clock.

thanks for your answer

C