New Contributor
Super ContributorNo, this isn't possible. You can't capture this much data inside the FPGA (limited buffer space) and as you've already found, sampling over the 24 MHz interface of JTAG is not sufficient. It might be better to look at the logic analyzer interface (LAI) to send the signals you want to see outside the device to a bench logic analyzer and use the huge storage available there.
Or you could look at a state-based trigger to have full control over how much buffer space each trigger stores in a segmented buffer to make most efficient use of the on-chip buffer.
New ContributorI'm pretty sure that's what I'm trying to do. I can send the signals to the LAI, and I could export them to a csv one at a time, but I'm trying to find a way to export them all at once. It seems like a trivial thing to do, but I can't figure it out! I attached an image of the interface after I've run an analysis.
Thanks for the help.
