signaltap trigger delay

Whenever I have had this sort of need, I've added a counter to the design. The simplest solution is to clear the counter on the initial trigger condition, and then use a simple trigger on the counter value.

Since the counter does not go anywhere, you need to add a synthesis constraint so that it does not get removed. For example, in VHDL ...

--- Quote Start ---

signal count : unsigned(15 downto 0);

attribute noprune : boolean;

attribute noprune of count : signal is true;

--- Quote End ---

Add the counter, synthesize your design, and then add count to your SignalTap II traces.

Cheers,

Dave