Honored Contributor
Honored Contributorhi David,
in my case i had to add this constrain in my top sdc file : # ************************************************************** # Create Clock # ************************************************************** create_clock -name {altera_reserved_tck} -period 30.303 [get_ports {altera_reserved_tck}] the values might be different in your case even though i think these are the ones to be used. the "altera_reserved_tck" is the one clock used to drive JTAG so constraining it can not harm your design. In my case this seemed to stop the weird results i was having on SignalTap. Tell me if you need more information. Yannick
