SignalTap issue

Hi guys,

has any of you figured out yet how to fix this random bug on ST ?

I'm currently using Quartus Prime Pro 16.0 with an Arria 10 chip and I firstly thought that this bugs where related to the fact i'm using an Engineering Sample thus JTAG might have been buggy. But reading what was posted on the forum i see that I'm not alone and it might no come from what i expected. I noticed that i sometimes compiled 3 times the same design with no changes between compilations and i would get this bug to occur on 1/2 or 3 of my signaltap instances independently and randomly. I'm really lossing time on recompiling my whole design just to get SignalTap to work once. Here are the different issues i get (note that i don't get any timing issues): -"waiting for clock" (the compile after that he'll find it ...)

-"Offloading data" when there is no trigger or triggering directly after i start

a capture on something mysterious.

- Oflloading some piece of data and not the full depth

I really feel like this problem might be related to Place and route or JTAG issues with my hardware.

If you found out , let me know.