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Altera_Forum
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9 years ago

SignalTap II Logic Analyzer: Maximum acquisition clock frequency - where to find?

Hi,

I'm searching the maximum acquisition frequency a SignalTap II can handle. I'm experimenting with viewing timing differences and so I need the clock as high as possible, but for some frequencies my design compiles properly, but the SignalTap simply doesn't trigger anymore... without warning or anything.

So I thought it might be a timing constraint for SignalTap and searched for it. The only information I can find is this:

--- Quote Start ---

The Quartus II static timing analysis tools show the maximum acquisition clock frequency at which you can run your design. Refer to the Timing Analysis section of the Compilation Report to find the maximum frequency of the logic analyzer clock.

--- Quote End ---

(from https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v3.pdf and exactly the same sentence in http://www.pcs.usp.br/~labdig/material/15.%20design%20debugging%20using%20the%20signaltap%20ii%20embedded%20logic%20analyzer.pdf)

But when I look for this value, I can't find it:

http://www.alteraforum.com/forum/attachment.php?attachmentid=12461&stc=1

Where do I have to look for in detail?

Thanks in advance.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Signatap is built out of logic resources so it's maximum frequency really depends on the design. If you exceed the Fmax of what the signaltap logic can handle then it'll show up in Timequest as a timing violation but there is no predefined Fmax in general for it. Whatever sampling clock you use is what you want to report to see if signaltap has any timing violations but judging by your screenshot you don't have a violation assuming that sample clock is properly defined in timing constraints.