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Altera_Forum
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9 years ago

SignalTap II issue

Hello, Here is debounce state machine: module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration localparam zero = 2'b...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Finally, Synchronization Register Chains resolved the problem.

I applied 2 flip-flops to sw input: 

	reg sw1, sw2;
	
	DFF sync1 (.d(sw), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw1));
	DFF sync2 (.d(sw1), .clk(clk), .clrn(1'b1), .prn(1'b1), .q(sw2));

and then applied sw2 to state machine (instead of sw).

However the signals sw1 and sw2 aren't accessible in signaltap ... only sync1, sync2.

I suppose that sync1 and sync2 are actually sw1 and sw2 ?

https://www.alteraforum.com/forum/attachment.php?attachmentid=13260