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Altera_Forum
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9 years ago

SignalTap II issue

Hello, Here is debounce state machine: module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration localparam zero = 2'b...
Altera_Forum's avatar
Altera_Forum
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9 years ago

You need a base clock constraint, create_clock, in your .sdc file for the design, as well as any related I/O timing constraints using set_input_delay and set_output_delay.