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Altera_Forum
Honored Contributor
9 years agoSignalTap II fails to acquire events
Hello, I'm using SignalTap II to debug and verify my Cyclone V SOC design. On the signal list there's an enumerated type VHDL FSM with 10 states. The FSM moves consecutively from one state ...
Altera_Forum
Honored Contributor
9 years agoDoesn't the "others" statement make the FSM safe ?
What extras does the tool add if you explicitly specify the "safe state machine" option ?