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Altera_Forum's avatar
Altera_Forum
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15 years ago

Signaltap Effects Design Operation!

I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i've been told it doesn't hurt to always include -add_delay to your set_input/output_delay constraints. you might want to check the TQ manual to see how this option is articulated