Signaltap Effects Design Operation!

Unbelieveable! Thank you very much "thepancake". I adapted your suggestions to my design and Timequest solved all the design problems.

Maybe not very important but one more thing is, when I write these constraints:

 
set_output_delay -clock { PLL_200MHz_inst|altpll_component|pll|clk } -reference_pin  2.4 
set_input_delay -clock { PLL_200MHz_inst|altpll_component|pll|clk }  -reference_pin  4.1 

Timequest gives this warning:

 
Warning: Assignment: 'set_input_delay -add_delay -clock  }] -reference_pin  4.100 ' had some problems but was accepted
Warning: Set_input_delay/set_output_delay has replaced one or more delays on port "SRAM_DQ". Please use -add_delay option.

Do you suggest using add_delay option or is it fine as the one in your example?

Thanks again for your help..