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Altera_Forum's avatar
Altera_Forum
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15 years ago

Signaltap Effects Design Operation!

I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ah, good point.

i think SSRAM should be fairly straight forward. you'll want to find the datasheet for the RAM, and maybe use another kit's constraints as an example (along with the TimeQuest documentation). here's the constraint from the CIII NEEK kit: 

##SSRAM Constraints
set_output_delay -clock  -reference_pin  2.4 
set_input_delay -clock   -reference_pin  4.1 
set_multicycle_path -from  -setup -end 2