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for the I/O, you should be able to take the constraints from a properly constrained example design and use them (with modified names) in your project. for internal logic, you will need to write your own constraints
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Unfortunately, the design examples all utilize Classic TA and there is no SDC file given. This sounds strange but Altera uses classic TA in reference designs although they suggest using Timequest.
Anyway, in fact the most critical external part is the SSRAM in the design.
Do you have any idea on how to determine the constraints for SSRAM?
Thanks for your help..
Honored Contributor
