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The classical timing analyzer can't see all possible timing violations, particularly with multiple timing domains.
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Thank you for your help Frank. You were right, Timequest solved some of my problems.
But I am new to timequest, so I don't really know how I can define all the constraints. I constrained only the main clock and PLL clocks for now. I guess the remaining problems are caused by undefined constraints. I use DE2-70 board and I am not sure about what the timing values should be set.
Is there any predetermined constraint values I can use or how can I determine them?
Honored Contributor
