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Altera_Forum's avatar
Altera_Forum
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15 years ago

Signaltap Effects Design Operation!

I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi pletz,

I've edit my post. Actually I mean the reverse. Design works normally with Signaltap enabled. When I disable it, the problems occur.

I use classic timing analyzer and there are no timing violations reported.

I use 2 clocks in the design (50M and 200MHz). Is there anything I should consider in multiclock case?

If you need to know any other information please ask me.

Thanks for your help.