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Altera_Forum's avatar
Altera_Forum
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15 years ago

Signaltap Effects Design Operation!

I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I am working on a design in Verilog. The design works normally without signaltap enabled. But, when I enable signaltap, the operation of the circuit changes. The results become erroneous. I think signaltap is an observer only, so it shouldn't change the design operation. Am I doing sth wrong?

Does anyone have an idea about this problem?

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Hi,

yes Signaltap is an "observer", but it has an influence to the synthesis, routing and placement. Did you get new timing violation when you use signaltap ?

Kind regards

GPK