Honored ContributorWhen I disable SignalTap in my design and recompile, the resulting design still has sld_hub, and I have trouble meeting timing because sld_hub itself cannot meet timing. I tried cutting the altera_internal_jtag~TCKUTAP timing path but timing got even worse. How come the sld_hub and other SignalTap blocks remain?
Honored ContributorHow are you removing it? Assignments -> Settings -> Signal Tap II Logic Analyzer(unchecking it). I think you can disable it within the .stp file so that it still exists so you can quickly tap nodes in a compiled design(i.e. the sld_hub is still there), which is not what you want.
Honored Contributorhttp://www.altera.com/support/kdb/solutions/rd09012005_325.html (http://www.altera.com/support/kdb/solutions/rd09012005_325.html)
sld_hub is there for NIOS on-chip debug and for NIOS JTAG UART, as well as signaltap.
