SignalTap and Timing

Good point, you can choose a level trigger rather than edge trigger. A signal that goes low to high in clk domain1 would soon be detected by other clock domains. Timing violation is possible but the level will soon settle and you may have one or more samples offset depending on lowest frequencies.

I don't see timing violation to be an issue here since the signaltap uses dual port ram and if in doubt you may synchronise that trigger signal to each domain then use some tricks to best align them in time.

When running signaltap each instance will be triggered by its own trigger moment.