SignalTap and Cyclone VI

There is a simple code

tp1 <= tp1_as;

process (fpga_reset_h, sys_clk_int) is

begin

if(fpga_reset_h = '1') then

--tp1 <= '0';

tp2 <= '0';

tp3 <= '0';

ser_txd <= '1';

elsif(rising_edge(sys_clk_int)) then

tp2 <= tp2_as;

tp3 <= tp3_as;

ser_txd <= ser_rxd;-- Synchronous Sequential Statement(s)

end if;

end process;

a1 : ENTITY work.spll

PORT MAP

(

areset => fpga_reset_h,

inclk0 => sys_clk,

c0 => sys_clk_int,

c1 => tp1_as,

c2 => tp2_as,

locked => tp3_as

);

There are no timing violations. SCD file contain correct clock constrains.

SignalTap connected to sys_clk_int and tp1, tp2, tp3.

SignalTap start off-loading data at some moment, but I don't see any graphical data. Pressing "Read Data" button gives result that looks like valid data at incorrect trigger condition

Thanks