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basically, you won't find a FF with a separate synchronous clear or set input, cause it's function couldn't distinguished from D input operation.
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But at the FPGA LE or ALM level, signals like synchronous clear do exist as separate LAB control signals as discussed in my previous post. Many or all device family handbooks have a figure showing how the LAB controls signals relate to the actual flip flop, and the Resource Property Editor diagram should show that detail for at least all LUT-based devices. The actual register might have only a D and clock enable input for the synchronous inputs, but from the user's perspective the LAB control signals like synchronous clear are distinct register inputs.
A way for David to see this is to list registers in the Node Finder, right click one of the registers, locate to the Resource Property Editor, and look at how the synchronous LAB control signals get combined into the D input inside the LE or ALM. (If the particular register being looked at didn't use those LAB control signals, the resources for them will still be shown, just grayed out.) The equivalent functionality like the mux and AND gate shown for Cyclone III can be accomplished inside the LUT(s) in front of what is listed as the register primitive D input in the equations; that's when the equations look like a synchronous clear is feeding the D input.
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