signal transfer in different clock domains

Hello,

there are two issues when processing signals from an unrelated clock domain:

1. Metastability

2. Setup and hold time violation

Metastability can occur as additional problem with timing violation, it can be avoided, when two cascaded registers are used to synchronize signals.

Setup and hold time violation is always present when interfacing external signals from unrelated clock domains respectively arbitrary events, thus it's the general case.

Consider a synchronous register and an external signal changing it's state at an arbitrary moment. Then, with a certain likelyhood, the transition occurs within the setup/hold intervall, which means that the resulting output is indetermined. This isn't actually an issue, but if an external signals is an input to more than one register, the system as a whole can react in an unwanted way.

Consider a 4 bit synchronous up counter with the asynchronous external signal as count enable. You would expect that the counter either counts +1 or 0. But if the setup/hold timing is violatet, it could e. g. count from 7 to 1 instead of 8, cause some registers "see" the count event and others don't. State machines could transition to an illegal state and at worst case be caught into it. Synchronisation of the external signal with a single register (or with two cascaded to avoid metastability) assures that all registers "see" the same external state.

If more than one signal shall be transfered consistently between clock domains, the situation is much more complicated. One solution could be gray-encoding.

Regards,

Frank