Signal Tap "program device to continue"

also:

check that your tweaks didn't include a licensed core that cause the design to be compiled in a time limited .sof instead of the regular one.

check in the assembler report that the .sof file was indeed written, and what path it is using

verify that the date of the .sof file you are uploading to the FPGA matches your last compile.

You can upload the .sof directly from the signaltap window by the way, it is just under the JTAG settings.