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AEsqu's avatar
AEsqu
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3 years ago

signal tap: pre-sythesis shall be named post-synthesis

Hello, It is possible to probe signal tap using pre-synthesis or post-fitting results from quartus. This is actually not correct, if you run compile only, you cannot probe the "pre-synthesis...
AEsqu's avatar
AEsqu
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3 years ago

No. run Analysis & Elaboration and you will see that you cannot probe the signal tap probes (delete the db before and try with a vqm from synplify). Quartus std edition.

sstrell's avatar
sstrell
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3 years ago
I wasn’t talking about a .vqm, which obviously has been synthesized by another tool. I’m talking about straight HDL code added to a Quartus project.
  • AEsqu's avatar
    AEsqu
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    3 years ago

    I use a mix of straight verilog/vhdl and one vqm.

    The vqm after elaboration shall be normally enough and not require a synthesis either.

    Please double check.

    • sstrell's avatar
      sstrell
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      3 years ago
      I’m not sure what you’re saying here but a .vqm by its definition is HDL already synthesized in another tool, so by its nature, it’s already post-synthesis. In Quartus to integrate it in a project, yes, you do have to perform synthesis.
      • AEsqu's avatar
        AEsqu
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        3 years ago

        So by selecting "signal tap: pre-sythesis", I still need to run a synthesis,

        as originally posted, correct?

        Which is strange to me, as Quartus properly compile and elaborate the RTL + the VQM without problem,

        so it shouldn't required a synthesis.

        As you stated, VQM is already synthesized, so why having to run the synthesis step again in quartus to include it in the elaborated database?