Contributor
Super ContributorNo. Pre-synthesis refers to signals exactly as they are defined in your HDL code. You don't need to perform full synthesis to get pre-synthesis signals for Signal Tap. Just run Analysis & Elaboration, which does not perform any synthesis. The compiler checks your HDL files and makes the pre-synthesis signals available for assignments like in the Assignment Editor and for tapping in Signal Tap.
ContributorNo. run Analysis & Elaboration and you will see that you cannot probe the signal tap probes (delete the db before and try with a vqm from synplify). Quartus std edition.
Super ContributorContributorI use a mix of straight verilog/vhdl and one vqm.
The vqm after elaboration shall be normally enough and not require a synthesis either.
Please double check.
