Forum Discussion
Hi,
I used a different version of Signal tap and I got this message
Internal Error: Sub-system: SDR, File: /quartus/sld/sdr/sdr_data_log.cpp, Line: 789
this->m_trigger_pos >= 0 && this->m_trigger_pos < samples_allocated
So i concluded that the trigger happens too early before enough samples are collected. I changed the trigger to a 19-bit counter. The trigger happened when the counter is equal to FFFF.
The previous error disappeared. However, I did a for loop to continously cature data from embedded logic and I received the data log with half the samples X and the rest of the samples are 0, except for the counter values which are increasing.
Any idea what is happening ?
Another general question on how signal tap works, if the triger condition is reached, would the embedded logic analyzer stop aquiring new data?or Does the RAM content that is transferred via JTAG remain constant till the trigger condition is repeated again ? I am trying to know the reason behind the data I get to solve the issue.
Best Regards,
Rana