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Altera_Forum's avatar
Altera_Forum
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16 years ago

Signal Tap inverting the Bits

Hello All,

I had added few signals to the signal tap ( Quartus II version 8.1, Signal tap version 8.1). The strange thing is that some of these signals which are active high in the design ( also verified in functional simulation) are seen as active low when viewed in the signal tap samples. Can anyone let me know why such a behaviour is seen? Has it got anything to do with how the signals are added ( selecting the nodes from Design Entry filter instead of Post Fitting filter)?

Thanks in advance,

Bipin

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    When a register must power-up high, synthesis will do something not-gate pushback. In essence, the register will still power-up low, and a not-gate will be put before and after it(and not gates can absorbed into LUTs for free, so there's generally no cost in doing this.) From a system level, this has the exact same behavior, but if you tap the actual register, you're tapping right before the not-gate after it, and it will look like it's the opposite of what it should be.

    The Synthesis report should have a list of all registers inverted, although it caps how many it reports to 100. This cap can be increased under Assignments -> Settings -> Analysis and Synthesis -> More Settings -> Number of Inverted Registers Reported...

    Personally, I would prefer to have the name slightly changed, like a ~inv added to the end, or something like that, so I don't have to go to a list. (Actually, once you've spent time looking at it, you get used to it and realize this occurs without going to the list). File an SR for this change if you'd like it too.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Is it a bus you are looking at? One thing you might check on (and I admit this may sound silly) is the order that signaltap is displaying the signals in a bus. Sometimes it orders the signals in a bus reverse from what you might expect.

    So if you are looking at a 2-bit bus and expecting to see "01" but are seeing "10", check to see if they're merely in the wrong order.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Please fix this. It needs to show up in SignalTap with a different name (such as the inversion symbol). I understand that there is not always a 1-to-1 mapping between hardware and HDL (optimizations, register inversions, etc), but if you're going to use the exact same signal name/label as written in HDL, it better have that signals behavior. This is just needlessly adding an extra step of looking up the inversion state in a report.

    Better yet, how about you just display it with the correct inversion, since it's guaranteed to have a not-gate tied to the register?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    If you select pre-synthesis signals in SignalTap instead of post-route then I doubt the inversions would show up. I always do pre-synthesis because it's just so much easier to look at, and the signals match your rtl. I've also never seen any signals inverted.