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Altera_Forum
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8 years ago

Signal Tap II Terasic Blaster Compatibility

System: Quartus Prime V16.1 HW: Cyclone V product board with JTAG header. FPGA Design: A Qsys system with JTAG to Avalon Master bridge, OnChip memory, Clock Source, and System ID Peripheral ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Thanks for the quick reply sstrell! I didn't realize that there would be conflict with simultaneous use of Signal Tap and System Console!

Your suggested sequence is what i've been doing. Configure the FPGA through Signal Tap, then start the analysis, then run System Console through Qsys then run the sequence of commands on System Console.

The reason i'm doing this is I'm having issues accessing the registers on my design using System Console, which is why i tried to debug it using Signal Tap. Without signal tap, I'll configure FPGA through Programmer, run System Console through Qsys, then run the same sequence as what's on my first post, then i get this register access error:

SEVERE: master_write_32: This transaction did not complete in 60 seconds. System Console is giving up.

Clock and reset are verified OK.

I've already scaled down my design to just a JTAG to Avalon Master Bridge with On Chip Memory. Might be my TCL command sequence???

Thanks!