Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSignal Tap II Terasic Blaster Compatibility
System: Quartus Prime V16.1 HW: Cyclone V product board with JTAG header. FPGA Design: A Qsys system with JTAG to Avalon Master bridge, OnChip memory, Clock Source, and System ID Peripheral ...
Altera_ForumHonored Contributor
Honored ContributorUsing both System Console and Signal Tap simultaneously on the same JTAG can be tricky. Have you tried connecting and starting the analysis in Signal Tap first before using System Console?
