Altera_Forum
Honored Contributor
14 years agoSignal Tap II error
Hi, all:
After I added SignalTap to the design, an error is reported when doing the compilation: Internal Error: Sub-system: VLGO, File: /quartus/neto/vlgo/vlgo_writer.cpp, Line: 3452 name_of_wire != NULL Stack Trace: 0x66D8 : VLGO_WRITER::write_input_port + 0x238 (NETO_VLGO) 0x94F2 : MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem) 0x5B45 : VLGO_GREYBOX::allow_netlist_generation + 0x845 (NETO_VLGO) 0x12939 : VLGO_WRITER::write_atom_input_port + 0x799 (NETO_VLGO) 0x80B5 : MEM_SEGMENT_INTERNAL::allocate + 0x95 (ccl_mem) 0x238B2 : _initptd + 0x15F (MSVCR90) 0x95EE9 : HDB_NAME_MGR::get_ischema + 0x69 (DB_HDB) 0x15B47 : VLGO_WRITER::write_atom_instance + 0x677 (NETO_VLGO) 0x1C996 : _Dinkum_std::use_facet<_Dinkum_std::num_put<char,_Dinkum_std::ostreambuf_iterator<char,_Dinkum_std::char_traits<char> > > > + 0x106 (dinkum_alt) 0x1BA37 : _Dinkum_std::operator<<<_Dinkum_std::char_traits<char> > + 0x167 (dinkum_alt) 0x6163F : `string' + 0xF (dinkum_alt) End-trace I've no idea what's going on with this problem? I'm looking forward someone to helping me. Thank you in advance.