Forum Discussion

hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Signal Tap example from Intel training course always fails timing

I am using Quartus Prime 21.1.0 Build 169 03/24/2021 SC Pro Edition to target a Cyclone 10 GX (10CX085) FPGA. I followed this Intel training course to set up Signal Tap: https://learning.intel.co...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @hcom ,

Any further update?

--- Quote Start ---

proc set_s10_false_path_constraint { } { if {$::TimeQuestInfo(family) == "Cyclone 10 GX"}

{ set_false_path -from "the node"

set_false_path -from "the node" } }

--- Quote End ---

Does the alternative provided above help?

Thanks.

Best regards,
Sheng

hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@ShengN_Intel I must admit, I am shocked by your suggestion. Of course, I could set timing ignores everywhere in my design and then I would never see any timing errors. But then I also wouldn't be constraining anything, so (without specific justification) this would be an incredibly bad thing to do.